FPGA Implementation of Quadrature Mirror Filter (QMF) For Equalizer Application of Wireless Communication Channel using VHDL

Authors:MUNJA SHIVA KUMAR, P.LAVANYA

0059-0064

Power Consumption in Fault Coverage Circuit with Efficient Hardware Utilization for Testing Applications

Authors:MOTHA SIREESHA, G.DEEPIKA

0065-0069

Genetic Algorithm Based Approach for Analysing Network-On-Chip

Authors:N. RAMALAKSHMI, N. HEMALATHA

0070-0075

Enhanced High Speed CAM Architecture using Parity Bit Based ML Sensing

Authors:M. SANTHOSHI, S. DHIVYA

0076-0080

Enhanced Launch-off Shift and Launch-off Capture Power Reduction in Transition Fault Testing

Authors:C. SHIRLY SALOMI, S. PREMALATHA

0081-0092

Frequency Divider Design using DFAL Technique

Authors:M.SURENDRA BABU, P.ASIYA TAPASWINI

0093-0096

Realization of Efficient Test Pattern Generator for Single Cycle Access Structure Testing

Authors:M.SHALEMURAJU, G.S.S.PRASAD

0097-0101

Low Power Adder Circuit Design Based on Approximation

Authors:M. RAVI JAGANNADH, CH. VASAVI SRIDEVI

0102-0107

Low Power Implementation using Clock and Power Gating

Authors:S. SANIL KUMAR PILLAI, M. KEDARESWARA RAO

0108-0112